Samanta jagannath (47 resultados)

Condición: New. pp. 72.

Condición: New. pp. 96.

Taschenbuch. Condición: Neu. UDSM CMOS Circuits | Delay & Power Models | Jagannath Samanta | Taschenbuch | 96 S. | Englisch | 2014 | LAP LAMBERT Academic Publishing | EAN 9783659523038 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

Condición: New. A brand new book in pristine condition. Showing zero signs of shelf wear, creases, or damage.

Condición: New. A brand new book in pristine condition. Showing zero signs of shelf wear, creases, or damage.

Condición: New.

Condición: New.

Condición: New.

Condición: As New. Unread book in perfect condition.

Condición: New. In English.

Condición: New. In English.

Condición: As New. Unread book in perfect condition.

Condición: New.

Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book provides insights into the 3rd International Conference on Communication, Devices and Computing (ICCDC 2021), which was held in Haldia, India, on August 16-18, 2021. It covers new ideas, applications, and the experiences of research engineers, scientists, industrialists, scholars, and students from around the globe. The proceedings highlight cutting-edge research on communication, electronic devices, and computing and address diverse areas such as 5G communication, spread spectrum systems, wireless sensor networks, and signal processing for secure communication, error control coding, printed antennas, analysis of wireless networks, antenna array systems, analog and digital signal processing for communication systems, frequency selective surfaces, radar communication, and substrate integrated waveguide and microwave passive components, which are key to state-of-the-art innovations in communication technologies.…

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book provides insights into the 3rd International Conference on Communication, Devices and Computing (ICCDC 2021), which was held in Haldia, India, on August 16-18, 2021. It covers new ideas, applications, and the experiences of research engineers, scientists, industrialists, scholars, and students from around the globe. The proceedings highlight cutting-edge research on communication, electronic devices, and computing and address diverse areas such as 5G communication, spread spectrum systems, wireless sensor networks, and signal processing for secure communication, error control coding, printed antennas, analysis of wireless networks, antenna array systems, analog and digital signal processing for communication systems, frequency selective surfaces, radar communication, and substrate integrated waveguide and microwave passive components, which are key to state-of-the-art innovations in communication technologies.…

Taschenbuch. Condición: Neu. Proceedings of the 4th International Conference on Communication, Devices and Computing | ICCDC 2023 | Dilip Kumar Sarkar (u. a.) | Taschenbuch | Lecture Notes in Electrical Engineering | xxii | Englisch | 2024 | Springer | EAN 9789819927128 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Paperback. Condición: Brand New. 789 pages. 9.25x6.10x1.57 inches. In Stock.

Condición: New.

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - The book is a collection of best selected research papers presented at the Fourth International Conference on Communication, Devices and Computing (ICCDC 2023). The book covers new ideas, applications and experiences of research engineers, scientists, industrialists, scholars and students from in and around the globe. It covers research contributions from communication technologies which are from the areas such as 5G communication, next-generation Wi-Fi, spread spectrum systems, satellite and high altitude platforms, radio over fiber techniques, wireless sensor networks, modulation and diversity technique, ad hoc and mesh networks, cognitive radio networking, optical wireless and visible light communications, signal processing for secure communication, millimeter wave and terahertz communication, design, control and management of optical network, error control coding and information theory, printed antennas, performance analysis of wireless network, smart antennas and space time processing.…

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology. 72 pp. Englisch.…

Condición: New. Print on Demand pp. 72 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Condición: New. PRINT ON DEMAND pp. 72.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts. 96 pp. Englisch.…

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology. …

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Samanta JagannathMr. Jagannath Samanta is serving as an Assistant Professor in the ECE dept at Haldia Institute of Technology, Haldia,WB. His research interest includes in Digital VLSI Design, Error Control Correction. Mr. A.K. Singh.…

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Samanta JagannathJ Samanta,currently working as Assistant Professor in the dept. of ECE at HIT, Haldia,India. He has received his B.Tech & M.Tech Degree from WBUT Kolkata. He has awarded Gold Medal during M.Tech course. His research . …

Condición: New. Print on Demand pp. 96 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts.…

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 72 pp. Englisch. …

Condición: New. PRINT ON DEMAND pp. 96.