ISBN: 9783844333817 - design of stereo vision processor: from algorithm to hardware implementation (10 resultados)

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Paperback. Condición: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock.

Taschenbuch. Condición: Neu. Design of Stereo Vision Processor | from algorithm to hardware implementation | Sang-Kyo Han | Taschenbuch | 56 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783844333817 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

Paperback. Condición: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents the VLSI architecture to achieve high-throughput and improved-quality stereo vision for real applications. The stereo vision processor generates gray-scale output images with depth information from input images taken by two CMOS Image Sensors (CIS). The depth estimator using the sum of absolute differences (SAD) algorithm as stereo matching technique is implemented on hardware by exploiting pipelining and parallelism. To produce depth maps with improved-quality at real-time, pre- and post-processing units are adopted, and to enhance the adaptability of the system to real environments, special function registers (SFRs) are assigned to vision parameters. The design using 0.18um standard CMOS technology can operate at 120MHz clock, achieving over 140 frames/sec depth maps with 320 by 240 image size and 64 disparity levels. Experimental results based on images taken in real world and the Middlebury data set will be presented. Comparison data with existing hardware systems and hardware specifications of the proposed processor will be given. 56 pp. Englisch.…

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents the VLSI architecture to achieve high-throughput and improved-quality stereo vision for real applications. The stereo vision processor generates gray-scale output images with depth information from input images taken by two CMOS Image Sensors (CIS). The depth estimator using the sum of absolute differences (SAD) algorithm as stereo matching technique is implemented on hardware by exploiting pipelining and parallelism. To produce depth maps with improved-quality at real-time, pre- and post-processing units are adopted, and to enhance the adaptability of the system to real environments, special function registers (SFRs) are assigned to vision parameters. The design using 0.18um standard CMOS technology can operate at 120MHz clock, achieving over 140 frames/sec depth maps with 320 by 240 image size and 64 disparity levels. Experimental results based on images taken in real world and the Middlebury data set will be presented. Comparison data with existing hardware systems and hardware specifications of the proposed processor will be given.…

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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Han Sang-KyoSang-Kyo Han received the B.E. degree in electrical engineering from KoreaUniversity, Seoul in 2002, and the M.S. degree in computer engineering from the University of Maryland, College Park in 2010, respectively. He work.…

Condición: New. PRINT ON DEMAND.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book presents the VLSI architecture to achieve high-throughput and improved-quality stereo vision for real applications. The stereo vision processor generates gray-scale output images with depth information from input images taken by two CMOS Image Sensors (CIS). The depth estimator using the sum of absolute differences (SAD) algorithm as stereo matching technique is implemented on hardware by exploiting pipelining and parallelism. To produce depth maps with improved-quality at real-time, pre- and post-processing units are adopted, and to enhance the adaptability of the system to real environments, special function registers (SFRs) are assigned to vision parameters. The design using 0.18um standard CMOS technology can operate at 120MHz clock, achieving over 140 frames/sec depth maps with 320 by 240 image size and 64 disparity levels. Experimental results based on images taken in real world and the Middlebury data set will be presented. Comparison data with existing hardware systems and hardware specifications of the proposed processor will be given.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch.…