Isbn: 9783659447525 - an improved mosfet i-v model and its application in nano-cmos circuits (9 resultados)

Condición: New. pp. 72.

Taschenbuch. Condición: Neu. An Improved Mosfet I-V Model and its Application in Nano-Cmos Circuits | Jagannath Samanta (u. a.) | Taschenbuch | 72 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659447525 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology. 72 pp. Englisch.…

Condición: New. Print on Demand pp. 72 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Condición: New. PRINT ON DEMAND pp. 72.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology. …

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Samanta JagannathMr. Jagannath Samanta is serving as an Assistant Professor in the ECE dept at Haldia Institute of Technology, Haldia,WB. His research interest includes in Digital VLSI Design, Error Control Correction. Mr. A.K. Singh.…

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -A compact MOSFET I-V model for estimating the drain current of sub-90nm MOSFET in the linear and saturation regions is proposed. It is a modification of nth-power law model introduced by Sakurai and Newton. The proposed model provides more accurate relationship between the channel length modulation and gate voltage in the saturation region. New parameters are introduced for better characterization of drain current of MOSFET at lower VGS and VDS. The proposed model is compared with Modified Sakurai-Newton (MSN) Current model and Extended-Sakurai-Newton (ESN) Compact MOSFET model, and it is found that the proposed model is much more accurate. The model provides precise estimation of drain current as well as the delay of a CMOS inverter. The drain characteristics predicted by the proposed model match with BSIM4v7 simulation with an average error of 1.33% and the delay estimations of CMOS inverter have an average error of 0.03 %( 0.12% maximum) in 90nm process technology.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 72 pp. Englisch. …