Isbn: 9781489979278 - digital system test and testable design: using hdl models and architectures (12 resultados)

PF. Condición: New.

Condición: New. In English.

Condición: New. pp. 452 Softcover reprint of the original 1st ed. 2011 edition NO-PA16APR2015-KAP.

Paperback. Condición: Brand New. reprint edition. 435 pages. 10.00x7.01x1.04 inches. In Stock.

Taschenbuch. Condición: Neu. Digital System Test and Testable Design | Using HDL Models and Architectures | Zainalabedin Navabi | Taschenbuch | xvii | Englisch | 2016 | Humana | EAN 9781489979278 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. …

Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies.…

Condición: new. Questo è un articolo print on demand.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware/software environment facilitates description of complex test programs and test strategies. 460 pp. Englisch.…

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. About the AuthorDr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments.…

Condición: New. Print on Demand pp. 452.

Condición: New. PRINT ON DEMAND pp. 452.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulateSimulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patternsDescribes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methodsSpringer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 460 pp. Englisch.…