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Añadir al carritoTaschenbuch. Condición: Neu. VLSI Synthesis of DSP Kernels | Algorithmic and Architectural Transformations | Sunil D. Sherlekar (u. a.) | Taschenbuch | xxiv | Englisch | 2010 | Springer US | EAN 9781441949042 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Idioma: Inglés
Publicado por Springer US, Springer New York, 2010
ISBN 10: 1441949046 ISBN 13: 9781441949042
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Añadir al carritoTaschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space. VLSI Synthesis of DSP Kernels presents the following: Six different target implementation styles - Programmable DSP-based implementation; Programmable processors with no dedicated hardware multiplier; Implementation using hardware multiplier(s) and adder(s); Distributed Arithmetic (DA)-based implementation; Residue Number System (RNS)-based implementation; and Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels. For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power; Automated and semi-automated techniques for applying each of these transformations; and Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style. VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.
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Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A critical step in the design of a DSP system is to identify for each of its components an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. This essential book covers architectures that offer varying degrees of programmability. 236 pp. Englisch.
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Añadir al carritoCondición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. A critical step in the design of a DSP system is to identify for each of its components an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. This essential book cove.
Idioma: Inglés
Publicado por Springer US, Springer New York Dez 2010, 2010
ISBN 10: 1441949046 ISBN 13: 9781441949042
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Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space.VLSI Synthesis of DSP Kernels presents the following: Six different target implementation styles - Programmable DSP-based implementation;Programmable processors with no dedicated hardware multiplier;Implementation using hardware multiplier(s) and adder(s);Distributed Arithmetic (DA)-based implementation;Residue Number System (RNS)-based implementation; andMultiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels.For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power;Automated and semi-automated techniques for applying each of these transformations; andClassification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style.VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 236 pp. Englisch.
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Añadir al carritoCondición: New. Print on Demand pp. 238 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
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Añadir al carritoCondición: New. PRINT ON DEMAND pp. 238.