Shouli yan (16 resultados)

Condición: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.

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Condición: New. pp. 112.

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Paperback. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Hardcover. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condición: As New. Unread book in perfect condition.

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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Low-Power High-Speed ADCs for Nanometer CMOS Integrationis about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. 112 pp. Englisch.…

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architecturesConcise and graphical explanation of key points in ADC/PLL design at both architecture and circuit level.…

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architecturesConcise and graphical explanation of key points in ADC/PLL design at both architecture and circuit level.…

Condición: New. Print on Demand pp. 112 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.

Condición: New. PRINT ON DEMAND pp. 112.