Burg andreas (115 resultados)

Condición: New. pp. 235.

Condición: New. pp. 248.

Paperback. Condición: Brand New. rep rev edition. 248 pages. 9.25x6.10x0.59 inches. In Stock.

Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.…

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.…

Hardcover. Condición: Gut. 33,5x25cm; 292 S. Hardcover. überw. Ill. Zustand: Sehr Gut, ungelesen (Innen); Einband (Außen) hat geringe Gebrauchsspuren; Seitlicher Schnitt ist in der Mitte geringfügig angestaubt; * Die Photos sind original von uns erstellt worden, u.a. erkennbar an einem kleinen weißen Stück Papier im oberen Schnitt. Ab und an verwenden Suchmaschinen Verlagsphotos, bei den Portalen selbst, werden aber nur unsere Originalphotos gezeigt.…

Gebundene Ausgabe. Condición: Neu. This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems. Sprache: Englisch Gewicht in Gramm: 489.…

Taschenbuch. Condición: Neu. VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design | 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers | Andreas Burg (u. a.) | Taschenbuch | IFIP Advances in Information and Communication Technology | x | Englisch | 2016 | Springer | EAN 9783662525296 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.…

Condición: As New. Unread book in perfect condition.

Condición: New.

Condición: New.

Condición: New.

Condición: As New. Unread book in perfect condition.

Condición: New. In English.

Condición: New.

Hardback. Condición: New. 1st ed. 2018. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.…

Condición: New. In English.

Condición: New.

Condición: New.

Condición: New.

Condición: New.

Hardcover. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condición: As New. Unread book in perfect condition.

Hardcover. Condición: Brand New. 146 pages. 9.25x6.25x0.50 inches. In Stock.

Condición: As New. Unread book in perfect condition.

Paperback. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condición: New. In German.

Gebundene Ausgabe. Condición: Neu. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. Sprache: Englisch Gewicht in Gramm: 354.…

Paperback. Condición: Brand New. reprint edition. 146 pages. 9.25x6.10x0.36 inches. In Stock.

Condición: New. pp. 146.