Andrzej j strojwas (48 resultados)
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Librería: Bay State Book Company, North Smithfield, RI, Estados Unidos de AmericaBay State Book Company
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EUR 42,72
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Condición: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Idioma: Inglés
Editorial: Kluwer Academic Publishers, Dordrecht, Holland, 1997
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- Primera edición
Librería: PsychoBabel & Skoob Books, Didcot, Reino UnidoPsychoBabel & Skoob Books
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EUR 32,23
Envío por EUR 14,62Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: 1 disponibles
hardcover. Condición: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
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Librería: Hamelyn, Madrid, M, EspañaHamelyn
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EUR 40,28
Envío por EUR 12,99Se envía de España a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Condición: Bueno. : Este libro trata sobre el diseño VLSI para la fabricación y la mejora del rendimiento. Cubre temas de ingeniería de sistemas e ingeniería informática. Es un recurso en línea que también está disponible en forma impresa. El libro forma parte de 'The Kluwer International Series in Engineering and Computer Scien…ce'. EAN: 9781461288169 Tipo: Libros Categoría: Tecnología|Ciencias Título: VLSI Design for Manufacturing: Yield Enhancement Autor: Stephen W. Director| Wojciech Maly| Andrzej J. Strojwas Editorial: Springer US Idioma: en Páginas: 308 Formato: Tapa blanda.
Vlsi Design for Manufacturing: Yield Enhancement
Director, Stephen W., With Wojciech Maly And Andrzej J. Strojwas
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Librería: BookDepart, Shepherdstown, WV, Estados Unidos de AmericaBookDepart
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EUR 58,01
Envío por EUR 7,30Se envía dentro de Estados Unidos de AmericaCantidad disponible: 1 disponibles
Hardcover. Condición: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page ed ges; otherwise in very good condition with clean text, firm binding.
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Librería: CONTINENTAL MEDIA & BEYOND, Ocala, FL, Estados Unidos de AmericaCONTINENTAL MEDIA & BEYOND
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EUR 71,22
Envío por EUR 6,04Se envía dentro de Estados Unidos de AmericaCantidad disponible: 1 disponibles
Condición: Used: Very Good. 1990 hardcover no dust jacket as issued volume 86 Name in book clean unmarked pages Published by Kluwer Academic 291 pages M-14.
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Librería: Mispah books, Redhill, SURRE, Reino UnidoMispah books
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EUR 56,63
Envío por EUR 29,25Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Hardcover. Condición: Like New. Like NewLIKE NEW. book.
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Librería: Basi6 International, Irving, TX, Estados Unidos de AmericaBasi6 International
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 98,38
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Condición: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
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Librería: Basi6 International, Irving, TX, Estados Unidos de AmericaBasi6 International
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EUR 98,38
Gastos de envío gratisSe envía dentro de Estados Unidos de AmericaCantidad disponible: 10 disponibles
Condición: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: Goodwill of Silicon Valley, SAN JOSE, CA, Estados Unidos de AmericaGoodwill of Silicon Valley
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EUR 96,79
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Condición: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
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Librería: -OnTimeBooks-, Phoenix, AZ, Estados Unidos de America-OnTimeBooks-
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EUR 103,10
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Condición: good. A copy that has been read, remains in good condition. All pages are intact, and the cover is intact. The spine and cover show signs of wear. Pages can include notes and highlighting and show signs of wear, and the copy can include "From the library of" labels or previous owner inscriptions. 100% GUARANTEE! Shipp…ed with delivery confirmation, if you're not satisfied with purchase please return item! Ships via media mail.
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Librería: GreatBookPrices, Columbia, MD, Estados Unidos de AmericaGreatBookPrices
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EUR 113,58
Envío por EUR 2,28Se envía dentro de Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New.
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Librería: BennettBooksLtd, Los Angeles, CA, Estados Unidos de AmericaBennettBooksLtd
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EUR 109,75
Envío por EUR 6,01Se envía dentro de Estados Unidos de AmericaCantidad disponible: 1 disponibles
hardcover. Condición: New. In shrink wrap. Looks like an interesting title.
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Librería: GreatBookPrices, Columbia, MD, Estados Unidos de AmericaGreatBookPrices
Contactar con el vendedorVendedor de 5 estrellasCondición: Usado - Como Nuevo
EUR 122,82
Envío por EUR 2,28Se envía dentro de Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: As New. Unread book in perfect condition.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
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EUR 116,74
Envío por EUR 14,01Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New. In.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
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EUR 116,74
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Condición: New. In.
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Librería: GreatBookPricesUK, Woodford Green, Reino UnidoGreatBookPricesUK
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EUR 116,72
Envío por EUR 17,55Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: Basi6 International, Irving, TX, Estados Unidos de AmericaBasi6 International
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 136,23
Gastos de envío gratisSe envía dentro de Estados Unidos de AmericaCantidad disponible: 10 disponibles
Condición: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
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Librería: Basi6 International, Irving, TX, Estados Unidos de AmericaBasi6 International
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 136,23
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Condición: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
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Librería: Buchpark, Trebbin, AlemaniaBuchpark
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EUR 35,62
Envío por EUR 105,00Se envía de Alemania a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Condición: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-…fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 132,60
Envío por EUR 9,50Se envía de Irlanda a Estados Unidos de AmericaCantidad disponible: 15 disponibles
Condición: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
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Librería: GreatBookPricesUK, Woodford Green, Reino UnidoGreatBookPricesUK
Contactar con el vendedorVendedor de 5 estrellasCondición: Usado - Como Nuevo
EUR 129,55
Envío por EUR 17,55Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: As New. Unread book in perfect condition.
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Librería: Books Puddle, New York, NY, Estados Unidos de AmericaBooks Puddle
Contactar con el vendedorVendedor de 4 estrellasCondición: Nuevo
EUR 143,74
Envío por EUR 3,45Se envía dentro de Estados Unidos de AmericaCantidad disponible: 4 disponibles
Condición: New. pp. 176.
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Librería: Kennys Bookstore, Olney, MD, Estados Unidos de AmericaKennys Bookstore
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 165,74
Envío por EUR 9,08Se envía dentro de Estados Unidos de AmericaCantidad disponible: 15 disponibles
Condición: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 166,09
Envío por EUR 14,01Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New. In.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 166,09
Envío por EUR 14,01Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New. In.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: California Books, Miami, FL, Estados Unidos de AmericaCalifornia Books
Contactar con el vendedorVendedor de 4 estrellasCondición: Nuevo
EUR 179,86
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Condición: New.
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Librería: AHA-BUCH GmbH, Einbeck, AlemaniaAHA-BUCH GmbH
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 112,77
Envío por EUR 62,18Se envía de Alemania a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (p…re-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Buchpark, Trebbin, AlemaniaBuchpark
Contactar con el vendedorVendedor de 5 estrellasCondición: Usado - Excelente
EUR 81,18
Envío por EUR 105,00Se envía de Alemania a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Condición: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Researc…h in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Mispah books, Redhill, SURRE, Reino UnidoMispah books
Contactar con el vendedorVendedor de 4 estrellasCondición: Usado - Como Nuevo
EUR 183,15
Envío por EUR 29,25Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Paperback. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Librería: Books Puddle, New York, NY, Estados Unidos de AmericaBooks Puddle
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EUR 210,67
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Condición: New. pp. 308.
