Andrzej j strojwas (41 resultados)
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Librería: Bay State Book Company, North Smithfield, RI, Estados Unidos de AmericaBay State Book Company
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EUR 43,50
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Condición: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Idioma: Inglés
Editorial: Kluwer Academic Publishers, Dordrecht, Holland 1997
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- Primera edición
Librería: PsychoBabel & Skoob Books, Didcot, Reino UnidoPsychoBabel & Skoob Books
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EUR 31,98
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hardcover. Condición: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W., with Wojciech Maly and Andrzej J. Strojwas
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Librería: BookDepart, Shepherdstown, WV, Estados Unidos de AmericaBookDepart
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EUR 59,06
Envío por EUR 7,43Se envía dentro de Estados Unidos de AmericaCantidad disponible: 1 disponibles
Hardcover. Condición: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page edges; otherwise in very good condition with clean text, firm binding.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: Goodwill of Silicon Valley, SAN JOSE, CA, Estados Unidos de AmericaGoodwill of Silicon Valley
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EUR 97,31
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Condición: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
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Librería: GreatBookPrices, Columbia, MD, Estados Unidos de AmericaGreatBookPrices
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EUR 115,65
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Condición: New.
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Librería: BennettBooksLtd, Los Angeles, CA, Estados Unidos de AmericaBennettBooksLtd
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EUR 111,75
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hardcover. Condición: New. In shrink wrap. Looks like an interesting title.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
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EUR 115,83
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Condición: New. In.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
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EUR 115,83
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Condición: New. In.
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Librería: GreatBookPricesUK, Woodford Green, Reino UnidoGreatBookPricesUK
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EUR 115,81
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Condición: New.
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Librería: Buchpark, Trebbin, AlemaniaBuchpark
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EUR 35,62
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Condición: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-…fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
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EUR 132,60
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Condición: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
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Librería: Books Puddle, New York, NY, Estados Unidos de AmericaBooks Puddle
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EUR 147,63
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Condición: New. pp. 176.
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Librería: GreatBookPricesUK, Woodford Green, Reino UnidoGreatBookPricesUK
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EUR 139,86
Envío por EUR 17,41Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: As New. Unread book in perfect condition.
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Librería: Mispah books, Redhill, SURRE, Reino UnidoMispah books
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EUR 130,31
Envío por EUR 29,02Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Hardcover. Condición: Like New. Like NewLIKE NEW. book.
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Librería: GreatBookPrices, Columbia, MD, Estados Unidos de AmericaGreatBookPrices
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EUR 161,42
Envío por EUR 2,32Se envía dentro de Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: As New. Unread book in perfect condition.
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Librería: Kennys Bookstore, Olney, MD, Estados Unidos de AmericaKennys Bookstore
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EUR 168,75
Envío por EUR 9,24Se envía dentro de Estados Unidos de AmericaCantidad disponible: 15 disponibles
Condición: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, b…iography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
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EUR 164,80
Envío por EUR 13,91Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New. In.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Librería: Ria Christie Collections, Uxbridge, Reino UnidoRia Christie Collections
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 164,80
Envío por EUR 13,91Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: Más de 20 disponibles
Condición: New. In.
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Librería: AHA-BUCH GmbH, Einbeck, AlemaniaAHA-BUCH GmbH
Contactar con el vendedorVendedor de 5 estrellasCondición: Nuevo
EUR 112,77
Envío por EUR 62,18Se envía de Alemania a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (p…re-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Buchpark, Trebbin, AlemaniaBuchpark
Contactar con el vendedorVendedor de 5 estrellasCondición: Usado - Excelente
EUR 81,18
Envío por EUR 105,00Se envía de Alemania a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Condición: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Researc…h in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Librería: Mispah books, Redhill, SURRE, Reino UnidoMispah books
Contactar con el vendedorVendedor de 4 estrellasCondición: Usado - Como Nuevo
EUR 185,31
Envío por EUR 29,02Se envía de Reino Unido a Estados Unidos de AmericaCantidad disponible: 1 disponibles
Paperback. Condición: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Librería: Books Puddle, New York, NY, Estados Unidos de AmericaBooks Puddle
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EUR 216,42
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Condición: New. pp. 308.
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Librería: Books Puddle, New York, NY, Estados Unidos de AmericaBooks Puddle
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EUR 216,93
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Condición: New. pp. 310.
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Librería: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
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EUR 201,60
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Condición: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . .
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Librería: moluna, Greven, Alemaniamoluna
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EUR 180,46
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Gebunden. Condición: New. One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufac.
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Librería: Kennys Bookstore, Olney, MD, Estados Unidos de AmericaKennys Bookstore
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EUR 257,21
Envío por EUR 9,24Se envía dentro de Estados Unidos de AmericaCantidad disponible: 15 disponibles
Condición: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . . Books ship from the… US and Ireland.
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Librería: Mispah books, Redhill, SURRE, Reino UnidoMispah books
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EUR 307,25
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Hardcover. Condición: Like New. Like New. book.
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Librería: Celler Versandantiquariat, Eicklingen, AlemaniaCeller Versandantiquariat
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Condición: Usado
EUR 26,00
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Kluwer, Boston, 1990. XII, 291 pages with some graphics, hardcover, (former library book)--- 750 Gramm.
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- Impresión bajo demanda
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AlemaniaBuchWeltWeit Ludwig Meier e.K.
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EUR 106,99
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabr…ication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing. 176 pp. Englisch.
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- Impresión bajo demanda
Librería: moluna, Greven, Alemaniamoluna
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EUR 92,27
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before… and after fabrication. Research in .
