Logical time work modeling de mallet frederic (6 resultados)
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Librería: preigu, Osnabrück, Alemaniapreigu
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Taschenbuch. Condición: Neu. Logical Time [at] Work for the Modeling and Analysis of Embedded Systems | Foundations of the UML/MARTE Time Model | Frederic Mallet | Taschenbuch | 124 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783843393881 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher La…ndstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AlemaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise… physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented. 124 pp. Englisch.
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Librería: moluna, Greven, Alemaniamoluna
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mallet FredericDr. Eng. Habil. Frederic Mallet is an Associate Professor in the Computer Science department at Nice-Sophia Antipolis University. He is a member of the AOSTE research unit, a joint team b…etween the I3S Laboratory and I.
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Librería: buchversandmimpf2000, Emtmannsberg, Alemaniabuchversandmimpf2000
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise phy…sical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 124 pp. Englisch.
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Librería: AHA-BUCH GmbH, Einbeck, AlemaniaAHA-BUCH GmbH
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise phys…ical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.
