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Logical Time @ Work for the Modeling and Analysis of Embedded Systems: Foundations of the UML/MARTE Time Model - Tapa blanda
Sinopsis
Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.
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Dr. Eng. Habil. Frederic Mallet is an Associate Professor in the Computer Science department at Nice-Sophia Antipolis University. He is a member of the AOSTE research unit, a joint team between the I3S Laboratory and INRIA Sophia Antipolis research center. He is a voting member of the OMG revision task forces for MARTE and SysML UML Profiles.
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems
Publicado por
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3843393885
ISBN 13: 9783843393881
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Tapa blanda
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mallet FredericDr. Eng. Habil. Frederic Mallet is an Associate Professor in the Computer Science department at Nice-Sophia Antipolis University. He is a member of the AOSTE research unit, a joint team between the I3S Laboratory and I. Nº de ref. del artículo: 5469196
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems
Publicado por
LAP LAMBERT Academic Publishing Jan 2011, 2011
ISBN 10: 3843393885
ISBN 13: 9783843393881
Nuevo
Taschenbuch
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented. 124 pp. Englisch. Nº de ref. del artículo: 9783843393881
Cantidad disponible: 2 disponibles
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems : Foundations of the UML/MARTE Time Model
Publicado por
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3843393885
ISBN 13: 9783843393881
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented. Nº de ref. del artículo: 9783843393881
Cantidad disponible: 1 disponibles
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems
Publicado por
LAP LAMBERT Academic Publishing Jan 2011, 2011
ISBN 10: 3843393885
ISBN 13: 9783843393881
Nuevo
Taschenbuch
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. Neuware -Logical time is a relaxed form of time promoted by synchronous languages that is functional, elastic (can be abstracted or refined), and multiform. All these properties make logical time adequate also at design time, whereas precise physical time annotations should only matter in later post-synthesis stages. The Clock Constraint Specification Language (CCSL) is a concrete language dedicated to the modeling and analysis of logical time properties. CCSL was initially defined as a companion for the time model of the UML profile for MARTE. It has now become a full-fledged domain-specific modeling language for capturing causal, chronological and timed relationships. It should complement other syntactic models to capture their underlying model of computation. This book starts by describing the historical models of concurrency that have inspired the construction of CCSL. Then, CCSL is introduced and used to build libraries dedicated to two emerging standard models from the automotive (East-ADL) and the avionic (AADL) domains. Finally, an observer-based technique to verify Esterel and VHDL implementations against CCSL specifications is presented.Books on Demand GmbH, Überseering 33, 22297 Hamburg 124 pp. Englisch. Nº de ref. del artículo: 9783843393881
Cantidad disponible: 2 disponibles
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Logical Time @ Work for the Modeling and Analysis of Embedded Systems: Foundations of the UML/MARTE Time Model
Publicado por
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3843393885
ISBN 13: 9783843393881
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Paperback. Condición: Like New. Like New. book. Nº de ref. del artículo: ERICA78738433938856
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