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Añadir al carritoHardcover. Condición: Very Good. No Jacket. Former library book; May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less.
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Añadir al carritoHardcover. Condición: Brand New. 146 pages. 9.25x6.25x0.50 inches. In Stock.
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Publicado por Springer International Publishing, Springer Nature Switzerland Jul 2017, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Idioma: Inglés
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
EUR 106,99
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Añadir al carritoBuch. Condición: Neu. Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 156 pp. Englisch.
Publicado por Springer International Publishing, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Idioma: Inglés
Librería: AHA-BUCH GmbH, Einbeck, Alemania
EUR 106,99
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Añadir al carritoBuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Publicado por Springer International Publishing, Springer International Publishing Mai 2018, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Idioma: Inglés
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
EUR 117,69
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Añadir al carritoTaschenbuch. Condición: Neu. Neuware Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 156 pp. Englisch.
Publicado por Springer International Publishing, Springer International Publishing, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Idioma: Inglés
Librería: AHA-BUCH GmbH, Einbeck, Alemania
EUR 117,69
Cantidad disponible: 1 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Librería: Revaluation Books, Exeter, Reino Unido
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Añadir al carritoPaperback. Condición: Brand New. reprint edition. 146 pages. 9.25x6.10x0.36 inches. In Stock.
Publicado por Springer International Publishing Jul 2017, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Idioma: Inglés
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
EUR 106,99
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Añadir al carritoBuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. 156 pp. Englisch.
Librería: Majestic Books, Hounslow, Reino Unido
EUR 132,33
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Publicado por Springer International Publishing, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Idioma: Inglés
Librería: moluna, Greven, Alemania
EUR 89,99
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Añadir al carritoGebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applicationsModels the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurementsDescribes various memory op.
Publicado por Springer International Publishing Mai 2018, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Idioma: Inglés
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
EUR 117,69
Cantidad disponible: 2 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. 156 pp. Englisch.
Librería: Biblios, Frankfurt am main, HESSE, Alemania
EUR 134,27
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Añadir al carritoCondición: New. PRINT ON DEMAND.
Publicado por Springer International Publishing, 2018
ISBN 10: 3319868551 ISBN 13: 9783319868554
Idioma: Inglés
Librería: moluna, Greven, Alemania
EUR 98,54
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Añadir al carritoCondición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applicationsModels the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurementsDescribes various memory op.
Publicado por Springer Nature Switzerland, 2017
ISBN 10: 3319604015 ISBN 13: 9783319604015
Idioma: Inglés
Librería: preigu, Osnabrück, Alemania
EUR 93,20
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Añadir al carritoBuch. Condición: Neu. Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip | Pascal Meinerzhagen (u. a.) | Buch | ix | Englisch | 2017 | Springer Nature Switzerland | EAN 9783319604015 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand.
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Añadir al carritoCondición: New. Print on Demand pp. 146.
Librería: Biblios, Frankfurt am main, HESSE, Alemania
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Añadir al carritoCondición: New. PRINT ON DEMAND pp. 146.