9783659746499 - performance evaluation of 3d sram architecture using coaxial tsv: research perspective de prasath r. arun; divya s. l. (8 resultados)
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Taschenbuch. Condición: Neu. Performance Evaluation of 3D SRAM Architecture using Coaxial TSV | Research Perspective | R. Arun Prasath (u. a.) | Taschenbuch | 68 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659746499 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osn…abrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -3D stacking of logic and memory devices is essential to keep the Moore's law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with m…ultiple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform. 68 pp. Englisch.
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Prasath R. ArunR. Arun Prasath, Faculty in the Department of Electronics and Communication Engineering at Anna University Regional Office, Madurai. Currently pursuing his Ph.D under faculty of Informati…on and Communication Engineerin.
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -3D stacking of logic and memory devices is essential to keep the Moore¿s law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multi…ple memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch.
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - 3D stacking of logic and memory devices is essential to keep the Moore's law ticking. In 3D integration, memory devices can be stacked on the top of processors. TSV based 3D memory architecture enables the reuse of logic dies with multip…le memory layers. Conventional 3D memory suffer from speed, power and yield overhead due to large parasitic load of TSV and cross layer PVT variations. In order to overcome these limitations, this paper the physical design of a semi master-slave (SMS) architecture of 3D SRAM which provides a constant-load logic-SRAM interface across various stacked layers and high tolerance for variations in cross-layer PVT is introduced. The SMS scheme is combined with self-timed differential-TSV (STDT) employing a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads in UMCP designs with scalable stacked layers and wide IO. This provides a universal memory capacity platform.
