9783659513619 - Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits de... (9 resultados)

Condición: New. pp. 296.

Taschenbuch. Condición: Neu. Design for Yield and Reliability for Nanometer CMOS Digital Circuits | Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits | Hassan Mostafa (u. a.) | Taschenbuch | 296 S. | Englisch | 2014 | LAP LAMBERT Academic Publishing | EAN 9783659513619 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

paperback. Condición: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops. 296 pp. Englisch.

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mostafa HassanDr. Hassan Mostafa received his PhD in Electrical and Computer Engineering from the University of Waterloo, Canada in 2011. Dr. Mostafa has worked as a research associate with Fujitsu labs (Japan), University of Toronto.

Condición: New. Print on Demand pp. 296 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.

Condición: New. PRINT ON DEMAND pp. 296.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 296 pp. Englisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.