Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits - Tapa blanda

Mostafa, Hassan; Anis, Mohab; Elmasry, Mohamed

 
9783659513619: Design for Yield and Reliability for Nanometer CMOS Digital Circuits: Statistical design, Soft errors modeling, Adaptive body bias, Negative capacitance circuits
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ISBN 10: 365951361X ISBN 13: 9783659513619
Editorial: LAP LAMBERT Academic Publishing, 2014

Sinopsis

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.

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Reseña del editor

The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to 12 GHz, and a single chip will contain over 40 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors (ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric yield and reliability of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random Access Memory (SRAM) and flip-flops.

Biografía del autor

Dr. Hassan Mostafa received his PhD in Electrical and Computer Engineering from the University of Waterloo, Canada in 2011. Dr. Mostafa has worked as a research associate with Fujitsu labs (Japan), University of Toronto, Canada, and IMEC (Belgium). He has authored/coauthored over 35 papers in international journals and conferences.

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2014
Idioma
Inglés
ISBN 10 
365951361X
ISBN 13 
9783659513619
Encuadernación
Tapa blanda
Número de páginas
296
Contacto del fabricante
no disponible
Persona responsable
no disponible