9783330331792 - cmos area efficient approximate arithmetic architectures de krishnasamy natarajan, vijeyakumar; sundaram, kalaiselvi; gurunathan, hamsathvani (6 resultados)
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Taschenbuch. Condición: Neu. CMOS Area Efficient Approximate Arithmetic Architectures | Vijeyakumar Krishnasamy Natarajan (u. a.) | Taschenbuch | 60 S. | Englisch | 2017 | LAP LAMBERT Academic Publishing | EAN 9783330331792 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[…at]preigu[dot]de | Anbieter: preigu.
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Approximate computation provide alternate solution to reduce energy consumption of high performance present day DSP application devices. Conventional multiplication and addition techniques consume a lot of energy. In this brief desi…gn of approximate arithmetic units for signal processing application is explored. First an approximate adder is proposed by changing the logic of basic full adder cell. The proposed adder cell has fewer transistor count compared to recent similar approach. Next, an approximate multiplier with low error is designed using lead one detection and selecting n/2 bits for an n bit input. The proposed n/2 bit approximate multiplier performs well in terms of error and power performance compared to recent similar approach. In continuation the approximate units are implemented in a Multiply-Accumulate(MAC) unit. The proposed approximate MAC unit provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Finally, the proposed MAC unit is implemented in filtering application to verify the functionality. 60 pp. Englisch.
CMOS Area Efficient Approximate Arithmetic Architectures
Vijeyakumar Krishnasamy Natarajan|Kalaiselvi Sundaram|Hamsathvani Gurunathan
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Krishnasamy Natarajan VijeyakumarK.N.Vijeyakumar has completed his ME in Applied Electronics at GCT, Coimbatore. He has completed his research in CMOS Processor Design for Signal and Image Processing Ap…plications. He has published re.
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Approximate computation provide alternate solution to reduce energy consumption of high performance present day DSP application devices. Conventional multiplication and addition techniques consume a lot of energy. In this brief design o…f approximate arithmetic units for signal processing application is explored. First an approximate adder is proposed by changing the logic of basic full adder cell. The proposed adder cell has fewer transistor count compared to recent similar approach. Next, an approximate multiplier with low error is designed using lead one detection and selecting n/2 bits for an n bit input. The proposed n/2 bit approximate multiplier performs well in terms of error and power performance compared to recent similar approach. In continuation the approximate units are implemented in a Multiply-Accumulate(MAC) unit. The proposed approximate MAC unit provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Finally, the proposed MAC unit is implemented in filtering application to verify the functionality.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch.
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Approximate computation provide alternate solution to reduce energy consumption of high performance present day DSP application devices. Conventional multiplication and addition techniques consume a lot of energy. In this brief design of… approximate arithmetic units for signal processing application is explored. First an approximate adder is proposed by changing the logic of basic full adder cell. The proposed adder cell has fewer transistor count compared to recent similar approach. Next, an approximate multiplier with low error is designed using lead one detection and selecting n/2 bits for an n bit input. The proposed n/2 bit approximate multiplier performs well in terms of error and power performance compared to recent similar approach. In continuation the approximate units are implemented in a Multiply-Accumulate(MAC) unit. The proposed approximate MAC unit provides significant improvement in power, area, and delay at the cost of little degrade in accuracy. Finally, the proposed MAC unit is implemented in filtering application to verify the functionality.
