ISBN: 9781402050800 - power management of digital circuits in deep sub-micron cmos technologies: 25 (springer series in advanced microelectronics, 25) (15 resultados)

127 figs., XVI, 183 p. Hardcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Stamped/gestempelt. Sprache: Englisch. …

Condición: As New. Unread book in perfect condition.

Condición: New.

Condición: New.

Condición: New. In English.

Condición: As New. Unread book in perfect condition.

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.…

Condición: New. pp. 204.

Condición: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.…

Condición: new. Questo è un articolo print on demand.

Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book provides an in-depth overview of design and implementation of leakage reduction techniques. The focus is on applicability, technology dependencies, and scalability. The book mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side. 200 pp. Englisch.…

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In-depth overview of design and implementation of leakage reduction techniquesFocus on applicability, technology dependencies, and scalabilityLink between system, circuit and physical levelNew design methodology (switch sizing for po.…

Buch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 204 pp. Englisch.…

Condición: New. Print on Demand pp. 204 Illus.

Condición: New. PRINT ON DEMAND pp. 204.