9780792398295 - computer-aided design techniques for low power sequential logic circuits: 387 (the springer international series in engineering and computer science, 387) de monteiro, jose; devadas, srinivas (15 resultados)
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Editorial: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A., 1997
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Condición: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well… as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.
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Condición: New. This text presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. Series: The Springer In…ternational Series in Engineering and Computer Science. Num Pages: 181 pages, biography. BIC Classification: TJFC; UY. Category: (P) Professional & Vocational; (XV) Technical / Manuals. Dimension: 234 x 156 x 12. Weight in Grams: 1030. . 1996. Hardback. . . . .
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Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as w…ell as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.
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Condición: New. This text presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. Series: The Springer In…ternational Series in Engineering and Computer Science. Num Pages: 181 pages, biography. BIC Classification: TJFC; UY. Category: (P) Professional & Vocational; (XV) Technical / Manuals. Dimension: 234 x 156 x 12. Weight in Grams: 1030. . 1996. Hardback. . . . . Books ship from the US and Ireland.
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Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat…dissipation as well as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research. 204 pp. Englisch.
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital syste…m determines its heat dissipation as .
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Buch. Condición: Neu. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits | José Monteiro (u. a.) | Buch | xvii | Englisch | 1996 | Springer | EAN 9780792398295 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter:… preigu Print on Demand.
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Buch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat diss…ipation as well as battery life. For some systems, power has become the most critical design constraint.Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines.Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle.Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit.Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 204 pp. Englisch.
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Condición: New. Print on Demand pp. 204 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
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Condición: New. PRINT ON DEMAND pp. 204.
