9780792395737 - Digit-Serial Computation: 316 (The Springer International Series in Engineering and Computer Science, 316) de Parhi, Keshab; Hartley, Richard (11 resultados)

Condición: New. In.

Condición: New. Describes the architecture, and the design and layout methods used in Parsifal: the silicon compiler developed at GEC's Corporate R&D Laboratory. This book discusses issues in digit-serial design in chapters on 'folding' and 'unfolding', and in chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 306 pages, biography. BIC Classification: PHDS; TJK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 19. Weight in Grams: 1390. . 1995. Hardback. . . . .

Condición: New. pp. 324 Index.

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.

Condición: New. Describes the architecture, and the design and layout methods used in Parsifal: the silicon compiler developed at GEC's Corporate R&D Laboratory. This book discusses issues in digit-serial design in chapters on 'folding' and 'unfolding', and in chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 306 pages, biography. BIC Classification: PHDS; TJK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 19. Weight in Grams: 1390. . 1995. Hardback. . . . . Books ship from the US and Ireland.

Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these syste.

Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory. 324 pp. Englisch.

Buch. Condición: Neu. Digit-Serial Computation | Richard Hartley (u. a.) | Buch | The Springer International Series in Engineering and Computer Science | xiii | Englisch | 1995 | Springer | EAN 9780792395737 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand.

Buch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 324 pp. Englisch.

Condición: New. Print on Demand pp. 324 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.

Condición: New. PRINT ON DEMAND pp. 324.