Zhiheng (110 resultados)

Condición: New.

Paperback or Softback. Condición: New. Causal Asymmetry & the Explanatory Constraint. Book.

Paperback. Condición: New.

Condición: As New. Unread book in perfect condition.

Condición: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.

Condición: New. In English.

PF. Condición: New.

Condición: New.

Hardcover. Condición: As New. 1st Edition. Rare 1st edition.

Condición: As New. Unread book in perfect condition.

Paperback. Condición: New.

PAP. Condición: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Condición: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.

Hardcover. Condición: New. Language:Chinese.Author:Zhang Zhiheng.Binding:HardCover.

Condición: New.

Condición: New.

Condición: Hervorragend. Zustand: Hervorragend | Sprache: Englisch | Produktart: Bücher | Causation is an asymmetric relation - if C causes E, then E does not cause C. In this book it is argued that: 1) Two major theories of causation - the regularity theory and the counterfactual theory - cannot adequately account for causal asymmetry; 2) Causal asymmetry consists in the explanatory asymmetry between cause and effect; 3) Generally, the notion of causation is dependent on the notion of explanation; in other words, explanation sets a conceptual constraint on causation. In reaching these conclusions, issues about simultaneous causation, backwards causation and absence causation are discussed.…

dvd. Condición: Sehr gut. Seiten; Das CD/DVD ist in einem gutem Zustand.Seiten sind sauber ohne Markierungen.Wir bieten eine 100% Geld-zurÃck-Garantie. CD-H16-101 Sprache: Deutsch Gewicht in Gramm: 500.

PAP. Condición: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Condición: New. In English.

Condición: New.

Condición: New. In English.

Condición: New.

Condición: New.

Condición: New. pp. 112.

Condición: As New. Unread book in perfect condition.

Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Low-Power High-Speed ADCs for Nanometer CMOS Integrationis about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.…

Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Low-Power High-Speed ADCs for Nanometer CMOS Integrationis about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. …

Paperback. Condición: Brand New. 108 pages. 9.00x6.00x0.26 inches. In Stock.

Condición: New. In English.