mahor vikas (57 resultados)

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Taschenbuch. Condición: Neu. Projekty uk¿adów VLSI odporne na wahania procesowe | Wysoce niezawodne i odporne na wahania procesowe projekty dynamicznej logiki CMOS | Vikas Mahor | Taschenbuch | Polnisch | 2026 | Wydawnictwo Nasza Wiedza | EAN 9786209960178 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. 80 pp. Englisch.

Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mahor VikasVikas Mahor, received the B.Tech. degree in electronics engineering from the Rajeev Gandhi Technical University, Bhopal, in 2007. In July 2012, he has been awarded with an M. Tech. degree in VLSI Design from Indian Institu.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Spanisch.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 80 pp. Englisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.

Taschenbuch. Condición: Neu. Process Variation Tolerant VLSI Designs | Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs | Vikas Mahor | Taschenbuch | 80 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659648946 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 68 pp. Französisch.

Paperback. Condición: new. Paperback. Les portes dynamiques constituent un excellent choix pour la conception de modules haute performance dans les microprocesseurs modernes. Leur seule limite reside dans leur marge de bruit relativement faible par rapport a celle des portes CMOS standard. Traditionnellement, ce probleme a ete resolu en utilisant un circuit de maintien pMOS qui compense le courant de fuite du reseau nMOS de mise a la masse. Dans les noeuds technologiques anterieurs, le circuit de maintien pouvait ameliorer la fiabilite des portes dynamiques avec une perte de performance mineure. Cependant, les tendances a la miniaturisation agressive de la technologie CMOS, associees a des niveaux croissants de variations de processus, ont reduit l'efficacite de l'approche traditionnelle par circuit de maintien. Ce probleme est plus grave dans les portes dynamiques a large fan-in en raison du grand nombre de dispositifs nMOS presentant des fuites connectes au noeud dynamique. Dans ce travail, une porte OU dynamique a large fan-in tolerante aux variations de processus est proposee, avec deux nouvelles conceptions de circuits de maintien capables de reduire la contention entre le circuit de maintien et le PDN et, par consequent, de reduire la dissipation de puissance et le retard. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Paperback. Condición: new. Paperback. As portas dinamicas tem sido uma excelente escolha no projeto de modulos de alto desempenho em microprocessadores modernos. A unica limitacao das portas dinamicas e a sua margem de ruido relativamente baixa, em comparacao com a das portas CMOS padrao. Tradicionalmente, esta questao tem sido resolvida atraves da utilizacao de um circuito de retencao pMOS que compensa a corrente de fuga da rede nMOS de pull-down. Nos nos tecnologicos anteriores, o circuito de retencao conseguia melhorar a fiabilidade das portas dinamicas com uma penalizacao de desempenho minima. No entanto, as tendencias de miniaturizacao agressivas da tecnologia CMOS, juntamente com os niveis crescentes de variacoes de processo, reduziram a eficacia da abordagem tradicional de retencao. Este problema e mais grave em portas dinamicas de ampla entrada devido ao grande numero de dispositivos nMOS com fuga ligados ao no dinamico. Neste trabalho, e proposta uma porta OR dinamica de ampla entrada tolerante a variacoes de processo com dois novos designs de mantenedor, capazes de reduzir a contencao entre o mantenedor e a PDN e, consequentemente, de reduzir a dissipacao de energia e o atraso. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Paperback. Condición: new. Paperback. Bramki dynamiczne stanowia doskonaly wybor przy projektowaniu modulow o wysokiej wydajnosci w nowoczesnych mikroprocesorach. Jedynym ograniczeniem bramek dynamicznych jest ich stosunkowo niski margines szumu w porownaniu ze standardowymi bramkami CMOS. Tradycyjnie problem ten rozwiazywano poprzez zastosowanie obwodu utrzymujacego pMOS, ktory kompensuje prad uplywowy sieci nMOS typu pull-down. We wczesniejszych wezlach technologicznych obwod utrzymujacy mogl poprawic niezawodnosc bramek dynamicznych przy niewielkim spadku wydajnosci. Jednak agresywne trendy skalowania technologii CMOS wraz z rosnacym poziomem zmiennosci procesowej zmniejszyly skutecznosc tradycyjnego podejscia opartego na obwodach utrzymujacych. Problem ten jest powazniejszy w bramkach dynamicznych o szerokim fan-in ze wzgledu na duza liczbe nieszczelnych urzadzen nMOS podlaczonych do wezla dynamicznego. W niniejszej pracy zaproponowano bramke dynamiczna OR o szerokim fan-in, odporna na zmiennosc procesu, z dwoma nowymi projektami obwodow utrzymujacych, ktore sa w stanie zmniejszyc konflikt miedzy obwodem utrzymujacym a PDN, a tym samym zmniejszyc rozpraszanie mocy i opoznienie. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Paperback. Condición: new. Paperback. Dynamische Gatter haben sich beim Entwurf von Hochleistungsmodulen in modernen Mikroprozessoren als hervorragende Wahl erwiesen. Die einzige Einschraenkung dynamischer Gatter ist ihre im Vergleich zu Standard-CMOS-Gattern relativ geringe Rauschmarge. Traditionell wurde dieses Problem durch den Einsatz einer pMOS-Keeper-Schaltung geloest, die den Leckstrom des Pull-down-nMOS-Netzwerks kompensiert. In frueheren Technologieknoten konnte die Keeper-Schaltung die Zuverlaessigkeit der dynamischen Gatter mit nur geringfuegigen Leistungseinbussen verbessern. Die aggressive Skalierung der CMOS-Technologie sowie zunehmende Prozessschwankungen haben jedoch die Wirksamkeit des traditionellen Keeper-Ansatzes verringert. Dieses Problem ist bei dynamischen Gates mit breitem Fan-In aufgrund der grossen Anzahl an leckenden nMOS-Bauelementen, die mit dem dynamischen Knoten verbunden sind, noch gravierender. In dieser Arbeit wird ein prozessvariationstolerantes dynamisches OR-Gate mit breitem Fan-In und zwei neuen Keeper-Designs vorgeschlagen, die in der Lage sind, die Konkurrenz zwischen dem Keeper und dem PDN zu verringern und somit die Verlustleistung und die Verzoegerung zu reduzieren. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Paperback. Condición: new. Paperback. I gate dinamici rappresentano una scelta eccellente nella progettazione di moduli ad alte prestazioni nei moderni microprocessori. L'unico limite dei gate dinamici e il loro margine di rumore relativamente basso rispetto a quello dei gate CMOS standard. Tradizionalmente, questo problema e stato risolto utilizzando un circuito di mantenimento pMOS che compensa la corrente di dispersione della rete nMOS pull-down. Nei nodi tecnologici precedenti, il circuito di mantenimento poteva migliorare l'affidabilita delle porte dinamiche con una penalizzazione minima in termini di prestazioni. Tuttavia, le tendenze di ridimensionamento aggressivo della tecnologia CMOS, insieme ai crescenti livelli di variazioni di processo, hanno ridotto l'efficacia dell'approccio tradizionale basato sul circuito di mantenimento. Questo problema e piu grave nei gate dinamici a fan-in ampio a causa del gran numero di dispositivi nMOS con dispersione collegati al nodo dinamico. In questo lavoro viene proposto un gate OR dinamico a fan-in ampio tollerante alle variazioni di processo con due nuovi design di keeper, in grado di ridurre la contesa tra il keeper e il PDN e quindi di ridurre la dissipazione di potenza e il ritardo. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Spanisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering.

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Paperback. Condición: new. Paperback. Les portes dynamiques constituent un excellent choix pour la conception de modules haute performance dans les microprocesseurs modernes. Leur seule limite reside dans leur marge de bruit relativement faible par rapport a celle des portes CMOS standard. Traditionnellement, ce probleme a ete resolu en utilisant un circuit de maintien pMOS qui compense le courant de fuite du reseau nMOS de mise a la masse. Dans les noeuds technologiques anterieurs, le circuit de maintien pouvait ameliorer la fiabilite des portes dynamiques avec une perte de performance mineure. Cependant, les tendances a la miniaturisation agressive de la technologie CMOS, associees a des niveaux croissants de variations de processus, ont reduit l'efficacite de l'approche traditionnelle par circuit de maintien. Ce probleme est plus grave dans les portes dynamiques a large fan-in en raison du grand nombre de dispositifs nMOS presentant des fuites connectes au noeud dynamique. Dans ce travail, une porte OU dynamique a large fan-in tolerante aux variations de processus est proposee, avec deux nouvelles conceptions de circuits de maintien capables de reduire la contention entre le circuit de maintien et le PDN et, par consequent, de reduire la dissipation de puissance et le retard. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.

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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Französisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering.

Taschenbuch. Condición: Neu. Conceptions VLSI tolérantes aux variations de processus | Conceptions de circuits logiques dynamiques CMOS hautement robustes et tolérantes aux variations de processus | Vikas Mahor | Taschenbuch | Französisch | 2026 | Editions Notre Savoir | EAN 9786209965296 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu Print on Demand.