T�tulo: Formal Semantics And Proof Techniques For Optimizing Vhdl Models (Hb)
Editor: Springer
Fecha de publicaci�n: 1998
Idioma: Ingl�s
ISBN 10: 0792383753
ISBN 13: 9780792383758
Encuadernaci�n: Encuadernaci�n de tapa dura
Estado: New

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Sinopsis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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