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Formal Semantics and Proof Techniques for Optimizing VHDL Models - Tapa dura

Umamageswaran, Kothanda; Wilsey, Philip A.; Pandey, Sheetanshu L.

 
9780792383758: Formal Semantics and Proof Techniques for Optimizing VHDL Models

Sinopsis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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Reseña del editor

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

"Sobre este título" puede pertenecer a otra edición de este libro.