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Detalles bibliogr�ficos

T�tulo

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Editor

Kluwer Academic Publishers

Fecha de publicaci�n

1998

Idioma

Ingl�s

ISBN 10

0792383753

ISBN 13

9780792383758

Encuadernaci�n

Hardcover

Estado

Like New

Cat�logos de vendedores

ELECTRONICS

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Sinopsis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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United Kingdom

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