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Sinopsis
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
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De la contraportada
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
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Networks on Chip
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Networks on Chip
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Networks on Chip
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Networks on Chip
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Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed . Nº de ref. del artículo: 4095044
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Networks on Chip
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Springer US, Chapman And Hall/CRC Jan 2003, 2003
ISBN 10: 1402073925
ISBN 13: 9781402073922
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation. 316 pp. Englisch. Nº de ref. del artículo: 9781402073922
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Networks on Chip
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Buch. Condición: Neu. Networks on Chip | Hannu Tenhunen (u. a.) | Buch | viii | Englisch | 2003 | Springer US | EAN 9781402073922 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Nº de ref. del artículo: 102567164
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Networks on Chip
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Kluwer Academic Publishers, 2003
ISBN 10: 1402073925
ISBN 13: 9781402073922
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Condición: New. As the number of processor cores and IP blocks integrated on a single chip is growing, a systematic approach to design the communication infrastructure becomes necessary. This book discusses the major issues from the physical integration to architecture to operating systems and application interfaces. Editor(s): Jantsch, Axel; Tenhunen, Hannu. Num Pages: 303 pages, biography. BIC Classification: UYF. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 235 x 155 x 19. Weight in Grams: 620. . 2003. Hardback. . . . . Nº de ref. del artículo: V9781402073922
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Networks on Chip
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Buch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation. Nº de ref. del artículo: 9781402073922
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Networks on Chip
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Springer US, Springer US Jan 2003, 2003
ISBN 10: 1402073925
ISBN 13: 9781402073922
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Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
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Buch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 316 pp. Englisch. Nº de ref. del artículo: 9781402073922
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