Networks on Chip - Tapa blanda

Sinopsis

Preface. Part I: System Design and Methodology. 1. Will Networks on Chip Close the Productivity Gap? A. Jantsch, H. Tenhunen. 2. A Design Methodology for NoC-based Systems; J.-P. Sommen, H. Heusala. 3. Mapping Concurrent Applications onto Architectural Platforms; A. Mihal, K. Keutzer. 4. Guaranteeing The Quality of Services in Networks on Chip; K. Goossens, J. Dielissen, J. van Meerbergen, P. Poplavko, A. Radulescu, E. Rijpkema, E. Waterlande, P. Wielage. Part II: Hardware and Basic Infrastructure. 5. On Packet Switched Networks for On-chip Communication; S. Kumar. 6. Energy-reliability Trade-off for NoCs; D. Bertozzi, L. Benini, G. De Micheli. 7. Testing Strategies for Networks on Chip; R. Ubar, J. Raik. 8. Clocking Strategies for Networks on Chip; J. Öberg. 9. A Parallel Computer as a NoC Region; M. Forseli. 10. An IP-Based On-Chip Packet-Switched Network; I. Saastamoinen, D. Sigilenza-Tortosa, J. Nurmi. Part III: Software and Application Interfaces. 11. Beyond the von Neumann Machine: Communication as the Driving Design Paradigm for MP-SoC from Software to Hardware; E. Verhulst. 12. NoC Application Programming Interfaces; Zhonghai Lu, R.Haukilahti. 13. Multi-level Software Validation for NoC; Sungjoo Yoo, G. Nicolescu, J. Bacivarov, W. Youssef, A. Bouchhima, A.A. Jerraya. 14. Software for Multiprocessor Networks on Chip; M. Grammatikakis, M. Coppola, F. Sensini.

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