White hardcover with black lettering on spine and upper board and contents in very good clean condition, showing minimal signs of wear. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T. N� de ref. del art�culo 249534

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Detalles bibliogr�ficos

T�tulo: Switch-Level Timing Simulation of MOS VLSI ...

Editorial: Kluwer Academic Publishers, Norwell, Massachusetts, U.S.A.

A�o de publicaci�n: 1989

Encuadernaci�n: hardcover

Condici�n: Very Good

Condici�n de la sobrecubierta: No Dust Jacket

Edici�n: First Edition.

Tipo de libro: Used

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Sinopsis:

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com� puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

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