9786205491133 - an efficient hardware architecture for multimedia encryption using dwt: multimedia encryption and authentication using the discrete wavelet transform de dhanalaxmi, banavath (5 resultados)
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Librería: preigu, Osnabrück, Alemaniapreigu
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Taschenbuch. Condición: Neu. An Efficient Hardware Architecture for Multimedia Encryption Using DWT | Multimedia Encryption and Authentication Using the Discrete Wavelet Transform | Banavath Dhanalaxmi | Taschenbuch | Englisch | 2022 | LAP LAMBERT Academic Publishing | EAN 9786205491133 | Verantwortliche Person für die EU: preig…u GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AlemaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parametrized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free… parameter in the design. It allows building a keyspace for lightweight multimedia encryption. The parametrization yields rational coefficients leading to an efficient fixed point hardware implementation. A clock speed of over 240 MHz was achieved on a Xilinx Virtex 5 FPGA. Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.The project will be implemented using HDL. Simulation will be done to verify the functionality and synthesis will be done to get the NETLIST. Simulation and synthesis will be done using Xilinx Tools. 108 pp. Englisch.
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Librería: AHA-BUCH GmbH, Einbeck, AlemaniaAHA-BUCH GmbH
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parametrized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free para…meter in the design. It allows building a keyspace for lightweight multimedia encryption. The parametrization yields rational coefficients leading to an efficient fixed point hardware implementation. A clock speed of over 240 MHz was achieved on a Xilinx Virtex 5 FPGA. Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.The project will be implemented using HDL. Simulation will be done to verify the functionality and synthesis will be done to get the NETLIST. Simulation and synthesis will be done using Xilinx Tools.
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Librería: moluna, Greven, Alemaniamoluna
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Kartoniert / Broschiert. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This book introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parametrized construction of the Discrete Wavelet Transform (DWT) compr…ession block is used to introduce a free parameter in the design.
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Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemaniabuchversandmimpf2000
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Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parametrized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free par…ameter in the design. It allows building a keyspace for lightweight multimedia encryption. The parametrization yields rational coefficients leading to an efficient fixed point hardware implementation. A clock speed of over 240 MHz was achieved on a Xilinx Virtex 5 FPGA. Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.The project will be implemented using HDL. Simulation will be done to verify the functionality and synthesis will be done to get the NETLIST. Simulation and synthesis will be done using Xilinx Tools.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 108 pp. Englisch.
