9786202923682 - Design of Proposed Hybrid 128-bit Parallel Adder/Subtractor de PRATHAP, JOSEPH ANTHONY (6 resultados)

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PAP. Condición: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condición: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 72 pp. Englisch.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtractor with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Parallel Adder/Subtractor. This paper compares the parametric values of power, delay, and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed parallel design exhibits low power and delay as the resolution of the design is increased. Also, the chip area is 0.3138µm2 for the 28T PAS circuit and 0.165 µm2 for the proposed 24T PAS circuitVDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 72 pp. Englisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtractor with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for the novel Parallel Adder/Subtractor. This paper compares the parametric values of power, delay, and area with the existing methods. The proposed design is developed using the Cadence Virtuoso Tool with the technology of 45 nm. The proposed parallel design exhibits low power and delay as the resolution of the design is increased. Also, the chip area is 0.3138µm2 for the 28T PAS circuit and 0.165 µm2 for the proposed 24T PAS circuit.