Isbn: 9783659457265 - programmable reed-solomon codec: design and implementation (5 resultados)

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  • Idioma: Inglés

    Editorial: Lap Lambert Academic Publishing, 2013

    3659457264 / 9783659457265

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    Librería: Revaluation Books, Exeter, Reino UnidoRevaluation Books

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    Paperback. Condición: Brand New. 64 pages. 8.66x5.91x0.15 inches. In Stock.

  • Idioma: Inglés

    Editorial: LAP LAMBERT Academic Publishing, 2013

    3659457264 / 9783659457265

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    Librería: preigu, Osnabrück, Alemaniapreigu

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    Taschenbuch. Condición: Neu. Programmable Reed-Solomon Codec | Design and Implementation | Jaydeb Bhaumik (u. a.) | Taschenbuch | 64 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659457265 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

  • Idioma: Inglés

    Editorial: LAP LAMBERT Academic Publishing Sep 2013, 2013

    3659457264 / 9783659457265

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    Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, AlemaniaBuchWeltWeit Ludwig Meier e.K.

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    Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform. 64 pp. Englisch.…

  • Idioma: Inglés

    Editorial: LAP LAMBERT Academic Publishing, 2013

    3659457264 / 9783659457265

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    Librería: moluna, Greven, Alemaniamoluna

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    Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Bhaumik JaydebDr.J. Bhaumik is working as an Asoc. Prof. in the Dept. of ECE, HIT. He obtained his PhD degree from IIT Kharagpur. He received his B.Tech & M.Tech from CU. His research areas: VLSI Design & Cryptography.Mr.A.S.Das is w. …

  • Idioma: Inglés

    Editorial: LAP LAMBERT Academic Publishing Sep 2013, 2013

    3659457264 / 9783659457265

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    Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemaniabuchversandmimpf2000

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    EUR 39,90

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    Cantidad disponible: 1 disponible

    Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 64 pp. Englisch.…