ISBN: 9783659246876 - compact modelling of dgmosfet's: carrier based compact model of long channel undoped & doped body symmetric dgmosfet's (4 resultados)

Taschenbuch. Condición: Neu. Compact Modelling of DGMOSFET's | Carrier based Compact Model of Long Channel Undoped & Doped body Symmetric DGMOSFET's | Neha Agarwal | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783659246876 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Double gate MOSFET is widely used for sub-50nm technology of transistor design .They have immunity to short channel effects, reduced leakage current and high scaling potential. The single gate Silicon on-insulator (SOI) devices give improved circuit speed and power consumption .But as the transistor size is reduced the close proximity between source and drain reduces the ability of the gate electrode to control the flow of current and potential distribution in the channel. To reduce SCE we need increase gate to channel coupling with respect to source/drain to channel coupling. This book presents the compact modeling of long channel undoped and doped symmetric double-gate MOSFET. The formulation starts with the solution of Poisson s equation which is then coupled to the Pao-Sah current equation to obtain the analytical drain-current model in terms of carrier concentration. The performance analysis of both the doped and undoped body symmetric DGMOS is done by using the model . Comparison of the two types of DGMOS is also done on the basis their electrical characteristics.…

Kartoniert / Broschiert. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Agarwal NehaNeha Agarwal, B.Tech (ECE) : Studied at UPTU University, U.P.,India, M.Tech (ECE) : Studied at GGSIP University,Delhi, India.Double gate MOSFET is widely used for sub-50nm technology of transistor design.…