9780128007273 - formal verification: an essential toolkit for modern vlsi design de seligman, erik; schubert, tom; kumar, m v achutha kiran (4 resultados)
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Librería: preigu, Osnabrück, Alemaniapreigu
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Taschenbuch. Condición: Neu. Formal Verification | An Essential Toolkit for Modern VLSI Design | Erik Seligman (u. a.) | Taschenbuch | Englisch | Morgan Kaufmann | EAN 9780128007273 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Paperback. Condición: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, , AlemaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification… (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Englisch.
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV)… enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
