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Sinopsis
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
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Acerca de los autores
Erik Seligman is currently a Senior Product Engineering Architect at Cadence Design Systems, where he helps to plan and support the Jasper Formal Verification tool suite. Previously he worked at Intel Corporation in Hillsboro, Oregon for over two decades, in a variety of positions involving software, design, simulation, and formal verification. In his spare time he hosts the “Math Mutation” podcast, and has served as an elected director on the Hillsboro school board.
Tom Schubert is on the Electrical and Computer Engineering faculty at Portland State University and directs a graduate track in Design Verification and Validation. Previously, he was at Intel Corporation for 17 years in Hillsboro, Oregon, where he managed Intel's largest pre-silicon validation formal verification team develop and apply FPV techniques on multiple generations of microprocessor designs. Tom received a PhD in Computer Science from the University of California, Davis.
M V Achutha Kiran Kumar is an Intel Fellow in the Design Engineering group at intel and leads the company’s Formal Verification Central Technology Office, one of the largest industrial Formal Verification teams in the world. He has over 19 years experience where he worked in various areas of the chip design cycle which includes RTL design, structural design, circuit design, simulation and various levels of validation including formal verification. He is the co-author of 'Formal Verification - An Essential toolkit for the Hardware Design'.
De la contraportada
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.
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Formal Verification An Essential Toolkit for Modern VLSI Design
Publicado por
Morgan Kaufmann, 2015
ISBN 10: 0128007273
ISBN 13: 9780128007273
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Librería: True Oak Books, Highland, NY, Estados Unidos de America
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Paperback. Condición: Good. Book contains highlighting from previous owner. Book contains markings and notes from previous owner. - Good overall condition. General wear. No major blemishes.; - We're committed to your satisfaction. We offer free returns and respond promptly to all inquiries. Your item will be carefully wrapped in bubble wrap and securely boxed. All orders ship on the same or next business day. Buy with confidence. Nº de ref. del artículo: HVD-26024-OS-0
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Formal Verification
Impresión bajo demandaLibrería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Englisch. Nº de ref. del artículo: 9780128007273
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Formal Verification
Impresión bajo demandaLibrería: moluna, Greven, Alemania
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a. Nº de ref. del artículo: 36539417
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Formal Verification : An Essential Toolkit for Modern VLSI Design
Impresión bajo demandaLibrería: AHA-BUCH GmbH, Einbeck, Alemania
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Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Nº de ref. del artículo: 9780128007273
Cantidad disponible: 2 disponibles
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Formal Verification: An Essential Toolkit for Modern Vlsi Design
Librería: Revaluation Books, Exeter, Reino Unido
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Paperback. Condición: Brand New. 408 pages. 9.00x7.50x1.00 inches. In Stock. Nº de ref. del artículo: 0128007273
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