High definition video requires substantial compression in order to be transmitted or stored economically. This volume presents VLSI design and chip implementation for high definition H.264/AVC video encoding using a state-of-the-art video application. Num Pages: 176 pages, 25 black & white tables, biography. BIC Classification: TBD; TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 12. Weight in Grams: 990. . 2010. Hardback. . . . . Books ship from the US and Ireland.

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Detalles bibliogr�ficos

T�tulo: VLSI Design for Video Coding
Editor: Springer-Verlag New York Inc.
Fecha de publicaci�n: 2010
Idioma: Ingl�s
ISBN 10: 1441909583
ISBN 13: 9781441909589
Encuadernaci�n: Encuadernaci�n de tapa dura
Estado: New

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Sinopsis

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

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VLSI Design for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.

Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;

Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;

Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;

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