High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.
This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.
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Back Cover Copy
VLSI Design for Video Coding
By:
Youn-Long Lin
Chao-Yang Kao
Jian-Wen Chen
Hung-Chih Kuo
High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.
This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.
Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;
Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;
Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;
"Sobre este título" puede pertenecer a otra edición de este libro.
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Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video. 176 pp. Englisch. Nº de ref. del artículo: 9781441909589
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Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encodingEmploys massively parallel processing to deliver up to 33 million pixels, with efficient design that can be prototyped via FPGA. Nº de ref. del artículo: 4172144
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Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video. Nº de ref. del artículo: 9781441909589
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