Provides detailed presentations of methodologies, algorithms and CAD tools for power modelling, estimation and analysis, synthesis and optimization at the logic level. It is designed for engineers, CAD professionals, and students with a basic knowledge of CMOS digital design and logic synthesis. Num Pages: 236 pages, biography. BIC Classification: TJF; UK. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 15. Weight in Grams: 1190. . 1997. Hardback. . . . .

N� de ref. del art�culo V9780792380764

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T�tulo: Logic Synthesis for Low Power VLSI Designs
Editor: Kluwer Academic Publishers
Fecha de publicaci�n: 1997
Idioma: Ingl�s
ISBN 10: 0792380762
ISBN 13: 9780792380764
Encuadernaci�n: Encuadernaci�n de tapa dura
Estado: New

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Sinopsis

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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