This is an ex-library book and may have the usual library/used-book markings inside.This book has hardback covers. In good all round condition. No dust jacket. Please note the Image in this listing is a stock photo and may not match the covers of the actual item,550grams, ISBN:9780792383758.

N� de ref. del art�culo 4137484

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Detalles bibliogr�ficos

T�tulo

Formal Semantics and Proof Techniques for Optimizing VHDL Models

Editor

Springer

Fecha de publicaci�n

1998

Idioma

Ingl�s

ISBN 10

0792383753

ISBN 13

9780792383758

Encuadernaci�n

Encuadernaci�n de tapa dura

Estado

Good

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Sinopsis

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Rese�a del editor

"Sobre este t�tulo" puede pertenecer a otra edici�n de este libro.

Descripci�n de la librer�a

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