Techniques for Power and Reliability Optimization of CMOS Logic: Power optimization, soft error tolerance improvement - Tapa blanda

Diril, Abdulkadir Utku

 
9783848409624: Techniques for Power and Reliability Optimization of CMOS Logic: Power optimization, soft error tolerance improvement
Tapa blanda
ISBN 10: 3848409623 ISBN 13: 9783848409624
Editorial: LAP LAMBERT Academic Publishing, 2012

Sinopsis

As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed. The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.

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Reseña del editor

As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed. The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.

Biografía del autor

Dr. Diril completed his Ph.D. in 2005 at Georgia Institute of Technology on the subject of low power design and reliability of CMOS circuits. After finishing his Ph.D., he worked at NVIDIA in the power optimization team. Then he joined Vivante Corporation as a design engineer. He is currently the Director of Hardware Engineering at Vivante.

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2012
Idioma
Inglés
ISBN 10 
3848409623
ISBN 13 
9783848409624
Encuadernación
Tapa blanda
Número de páginas
108
Contacto del fabricante
no disponible
Persona responsable
no disponible