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Sinopsis
In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.
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In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.
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It describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.
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Low Power Flash ADC
Publicado por
LAP LAMBERT Academic Publishing Aug 2011, 2011
ISBN 10: 3845440848
ISBN 13: 9783845440842
Nuevo
Taschenbuch
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC. 80 pp. Englisch. Nº de ref. del artículo: 9783845440842
Cantidad disponible: 2 disponibles
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Low Power Flash ADC
Publicado por
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3845440848
ISBN 13: 9783845440842
Nuevo
Tapa blanda
Librería: moluna, Greven, Alemania
Calificación del vendedor: 5 de 5 estrellas
Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Subba Reddy MurraIt describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.In this project, a new design for a low power CMOS flash Analog-to-Digital Conve. Nº de ref. del artículo: 5482784
Cantidad disponible: Más de 20 disponibles
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Low Power Flash ADC : VLSI Technology
Publicado por
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3845440848
ISBN 13: 9783845440842
Nuevo
Taschenbuch
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC. Nº de ref. del artículo: 9783845440842
Cantidad disponible: 1 disponibles
Imagen del vendedor
Low Power Flash ADC
Publicado por
LAP LAMBERT Academic Publishing Aug 2011, 2011
ISBN 10: 3845440848
ISBN 13: 9783845440842
Nuevo
Taschenbuch
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. Neuware -In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.Books on Demand GmbH, Überseering 33, 22297 Hamburg 80 pp. Englisch. Nº de ref. del artículo: 9783845440842
Cantidad disponible: 2 disponibles