Effect of Underlap On Device Performance of GaN Based DG-MOSFET - Tapa blanda

Hasan, Md. Rokib; Al Faisal, Saud; Hossain, Marwan

 
9783659920134: Effect of Underlap On Device Performance of GaN Based DG-MOSFET
Tapa blanda
ISBN 10: 3659920134 ISBN 13: 9783659920134
Editorial: LAP LAMBERT Academic Publishing, 2016

Sinopsis

GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

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Reseña del editor

GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Biografía del autor

I am Md. Rokib Hasan. My home town is Mymensingh, Bangladesh. I have completed my B.Sc. in Electrical and Electronics Engineering from American International University- Bangladesh (AIUB).I was nominated as a General Secretary of "IEEE AIUB STUDENT BRANCH" for 2015.I am an active member of IEEE for three years(2014-2016).

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Editorial
LAP LAMBERT Academic Publishing
Año de publicación
2016
Idioma
Inglés
ISBN 10 
3659920134
ISBN 13 
9783659920134
Encuadernación
Tapa blanda
Número de páginas
68
Contacto del fabricante
no disponible
Persona responsable
no disponible