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Sinopsis
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
"Sinopsis" puede pertenecer a otra edición de este libro.
Reseña del editor
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
"Sobre este título" puede pertenecer a otra edición de este libro.
- EditorialSpringer
- Año de publicación2013
- ISBN 10 1475770367
- ISBN 13 9781475770360
- EncuadernaciónTapa blanda
- IdiomaInglés
- Número de páginas600
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automatio. Nº de ref. del artículo: 4207669
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Logic Synthesis and Verification Algorithms
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ISBN 10: 1475770367
ISBN 13: 9781475770360
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs. 600 pp. Englisch. Nº de ref. del artículo: 9781475770360
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Logic Synthesis and Verification Algorithms
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Logic Synthesis and Verification Algorithms
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ISBN 10: 1475770367
ISBN 13: 9781475770360
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Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs. Nº de ref. del artículo: 9781475770360
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Logic Synthesis and Verification Algorithms
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Springer-Verlag New York Inc., 2013
ISBN 10: 1475770367
ISBN 13: 9781475770360
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Logic Synthesis and Verification Algorithms
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ISBN 10: 1475770367
ISBN 13: 9781475770360
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Taschenbuch. Condición: Neu. Neuware -Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.A unique feature of this text is the large collection of solved problems.Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 600 pp. Englisch. Nº de ref. del artículo: 9781475770360
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