Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling - Tapa dura

Mandal, Ayan; Mahapatra, Rabi; Khatri, Sunil P.

 
9781461494041: Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling
Tapa dura
ISBN 10: 1461494044 ISBN 13: 9781461494041
Editorial: Springer, 2013

Sinopsis

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

"Sinopsis" puede pertenecer a otra edición de este libro.

De la contraportada

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

"Sobre este título" puede pertenecer a otra edición de este libro.

Editorial
Springer
Año de publicación
2013
Idioma
Inglés
ISBN 10 
1461494044
ISBN 13 
9781461494041
Encuadernación
Tapa dura
Número de páginas
160
Contacto del fabricante
no disponible
Persona responsable
CMN Printpool Inh. Mathis Neumann
https://www.also.com/ec/cms5/en_6000/6000/index.jsp

Friedrich-Karl-Str. 9
Hamburg
Alemania

Otras ediciones populares con el mismo título

9781493948178: Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling

Edición Destacada

ISBN 10:  1493948172 ISBN 13:  9781493948178
Editorial: Springer, 2016
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