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From Contamination to Defects, Faults and Yield Loss: Simulation and Applications: 5 (Frontiers in Electronic Testing) - Tapa blanda
Libro 27 de 36: Frontiers in Electronic Testing
Sinopsis
Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.
Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.
From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
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Reseña del editor
Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
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From Contamination to Defects, Faults and Yield Loss
Librería: Hamelyn, Madrid, M, España
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Condición: Bueno. : A lo largo de los años, ha habido un gran aumento en la funcionalidad disponible en un solo circuito integrado. Esto se ha logrado principalmente mediante un impulso continuo hacia tamaños de características más pequeños, matrices más grandes y una mejor eficiencia de empaquetado. Sin embargo, esta mayor funcionalidad también ha resultado en aumentos sustanciales en la inversión de capital necesaria para construir instalaciones de fabricación. Dada una inversión tan alta, es fundamental para los fabricantes de circuitos integrados reducir los costos de fabricación y obtener un mejor retorno de su inversión. El método más obvio para reducir el costo de fabricación por matriz es mejorar el rendimiento de fabricación. La investigación e ingeniería modernas de VLSI (que incluyen el diseño, la fabricación y las pruebas) abarcan una gama muy amplia de disciplinas como la química, la física, la ciencia de los materiales, el diseño de circuitos, las matemáticas y la informática. Debido a esta diversidad, el campo de VLSI se ha fracturado en una serie de subdominios separados con poca o ninguna interacción entre ellos. Este es el caso de las relaciones entre las pruebas y la fabricación. De la contaminación a los defectos, las fallas y la pérdida de rendimiento: la simulación y las aplicaciones se centra en el núcleo de la interfaz entre la fabricación y las pruebas, es decir, la relación contaminación-defecto-falla. La comprensión de esta relación puede conducir a mejores soluciones de muchos problemas de fabricación y pruebas. Se desarrollan y presentan modelos de mecanismos de falla que se pueden utilizar para estimar con precisión la probabilidad de diferentes fallas para un circuito integrado dado. Esta información es fundamental para resolver aplicaciones clave relacionadas con el rendimiento, como el análisis de fallas, el modelado de fallas y la fabricación de diseños. EAN: 9781461285953 Tipo: Libros Categoría: Tecnología Título: From Contamination to Defects, Faults and Yield Loss Autor: Jitendra B. Khare Idioma: eng Páginas: 168 Formato: Tapa blanda. Nº de ref. del artículo: Happ-2026-07-02-462e3e07
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From Contamination to Defects, Faults and Yield Loss (eng)
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From Contamination to Defects, Faults and Yield Loss: Simulation and Applications (Frontiers in Electronic Testing)
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From Contamination to Defects, Faults and Yield Loss
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Springer US, Springer New York Sep 2011, 2011
ISBN 10: 146128595X
ISBN 13: 9781461285953
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Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing. 172 pp. Englisch. Nº de ref. del artículo: 9781461285953
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From Contamination to Defects, Faults and Yield Loss
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Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this gre. Nº de ref. del artículo: 4191160
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From Contamination to Defects, Faults and Yield Loss
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From Contamination to Defects, Faults and Yield Loss
Publicado por
Springer US, Springer New York Sep 2011, 2011
ISBN 10: 146128595X
ISBN 13: 9781461285953
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Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
Calificación del vendedor: 5 de 5 estrellas
Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield.Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.Springer-Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 172 pp. Englisch. Nº de ref. del artículo: 9781461285953
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From Contamination to Defects, Faults and Yield Loss : Simulation and Applications
Librería: AHA-BUCH GmbH, Einbeck, Alemania
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Taschenbuch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Over the years there has been a large increase in the functionality available on a single integrated circuit. This has been mainly achieved by a continuous drive towards smaller feature sizes, larger dies, and better packing efficiency. However, this greater functionality has also resulted in substantial increases in the capital investment needed to build fabrication facilities. Given such a high level of investment, it is critical for IC manufacturers to reduce manufacturing costs and get a better return on their investment. The most obvious method of reducing the manufacturing cost per die is to improve manufacturing yield. Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing. From Contamination to Defects, Faults and Yield Loss: Simulation and Applications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems. Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing. Nº de ref. del artículo: 9781461285953
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