Verification by Error Modeling: Using Testing Techniques in Hardware Verification: 25 (Frontiers in Electronic Testing, 25) - Tapa dura

Libro 4 de 36: Frontiers in Electronic Testing

Radecka, Katarzyna; Zilic, Zeljko

 
9781402076527: Verification by Error Modeling: Using Testing Techniques in Hardware Verification: 25 (Frontiers in Electronic Testing, 25)

Sinopsis

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

"Sinopsis" puede pertenecer a otra edición de este libro.

Críticas

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

Reseña del editor

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

"Sobre este título" puede pertenecer a otra edición de este libro.

Otras ediciones populares con el mismo título

9781441954022: Verification by Error Modeling: Using Testing Techniques in Hardware Verification: 25 (Frontiers in Electronic Testing)

Edición Destacada

ISBN 10:  1441954023 ISBN 13:  9781441954022
Editorial: Springer, 2010
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