Nano-Interconnect Materials and Models for Next Generation Integrated Circuit Design - Tapa dura

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Sandip Bhattacharya received his Ph.D. (Eng.) degree from the Indian Institute of Engineering Science and Technology (IIEST), India, in 2017. From October 2017 to December 2020, he worked as a postdoctoral researcher at the HiSIM research center, Hiroshima University, Japan. He is currently working as an Associate Professor and Head of the Department of Electronics and Communication Engineering at SR University, Warangal, Telangana, India. His current research interests are nano device and interconnect modeling.

J. Ajayan received his B.Tech. degree in Electronics and Communication Engineering from Kerala University in 2009, and M.Tech. and Ph.D. degrees in Electronics and Communication Engineering from Karunya University, Coimbatore, India, in 2012 and 2017, respectively. He is an Associate Professor in the Department of Electronics and Communication Engineering at SR University, Telangana, India. He has published more than 100 research articles in various journals and international conferences. He has published two books, more than ten book chapters, and has two patents. He is a reviewer of more than 30 journals for various publishers. He was the Guest Editor for several of the special issues. His areas of interest are microelectronics, semiconductor devices, nanotechnology, RF integrated circuits, and photovoltaics.

Fernando Avila Herrera has worked in the field of academic and semiconductor industry. He has involved with the modeling and characterization of semiconductor devices, especially MOSFETs. Further, he has experience in device reliability modeling, model parameter extraction, Verilog-A, TCAD, and EDA tools. He also has experience in HiSIM family models for parameter extraction and physics modeling and FPGA programming. He has collaborated with different groups for developing compact models.