Book by Joobbani R
"Sinopsis" puede pertenecer a otra edición de este libro.
Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors.
"Sobre este título" puede pertenecer a otra edición de este libro.
GRATIS gastos de envío en Estados Unidos de America
Destinos, gastos y plazos de envíoEUR 4,41 gastos de envío en Estados Unidos de America
Destinos, gastos y plazos de envíoLibrería: Friends of the Library Bookstore, Eau Claire, WI, Estados Unidos de America
Hardcover. Condición: Good. No Jacket. A used textbook that has a coffee-colored stain on the top edge. The pages are otherwise clean and unmarked. The spine is slightly cocked and shows some shelf wear on the top and bottom. A few handling marks on the back cover. The corners are sharp. 159 p. "Routing of VLSI chips is an important, time-consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality." Not ex-library. Shelf: B-1. Nº de ref. del artículo: 220915JS
Cantidad disponible: 1 disponibles
Librería: Ammareal, Morangis, Francia
Hardcover. Condición: Bon. Ancien livre de bibliothèque. Traces d'usure sur la couverture. Edition 1986. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Good. Former library book. Signs of wear on the cover. Edition 1986. Ammareal gives back up to 15% of this item's net price to charity organizations. Nº de ref. del artículo: E-840-427
Cantidad disponible: 1 disponibles
Librería: Ammareal, Morangis, Francia
Hardcover. Condición: Très bon. Ancien livre de bibliothèque. Légères traces d'usure sur la couverture. Salissures sur la tranche. Edition 1985. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Very good. Former library book. Slight signs of wear on the cover. Stains on the edge. Edition 1985. Ammareal gives back up to 15% of this item's net price to charity organizations. Nº de ref. del artículo: E-573-941
Cantidad disponible: 1 disponibles
Librería: BOOKWEST, Phoenix, AZ, Estados Unidos de America
Hardcover. Condición: New. US SELLER SHIPS FAST FROM USA. Nº de ref. del artículo: 135C2-089838205X
Cantidad disponible: 1 disponibles
Librería: Lucky's Textbooks, Dallas, TX, Estados Unidos de America
Condición: New. Nº de ref. del artículo: ABLIING23Mar2317530032013
Cantidad disponible: Más de 20 disponibles
Librería: Ria Christie Collections, Uxbridge, Reino Unido
Condición: New. In. Nº de ref. del artículo: ria9780898382051_new
Cantidad disponible: Más de 20 disponibles
Librería: moluna, Greven, Alemania
Gebunden. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ign. Nº de ref. del artículo: 5982383
Cantidad disponible: Más de 20 disponibles
Librería: AHA-BUCH GmbH, Einbeck, Alemania
Buch. Condición: Neu. Druck auf Anfrage Neuware - Printed after ordering - Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors. Nº de ref. del artículo: 9780898382051
Cantidad disponible: 1 disponibles
Librería: THE SAINT BOOKSTORE, Southport, Reino Unido
Hardback. Condición: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 571. Nº de ref. del artículo: C9780898382051
Cantidad disponible: Más de 20 disponibles
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
Buch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Routing of VLSI chips is an important, time consuming, and difficult problem. The difficulty of the problem is attributed to the large number of often conflicting factors that affect the routing quality. Traditional techniques have approached routing by ignoring some of these factors and imposing unnecessary constraints in order to make routing tractable. In addition to the imposition of these restrictions, which simplify the problems to a degree but at the same time reduce the routing quality, traditional approaches use brute force. They often transform the problem into mathematical or graph problems and completely ignore the specific knowledge about the routing task that can greatly help the solution. This thesis overcomes some of the above problems and presents a system that performs routing close to what human designers do. In other words it heavily capitalizes on the knowledge of human expertise in this area, it does not impose unnecessary constraints, it considers all the different factors that affect the routing quality, and most importantly it allows constant user interaction throughout the routing process. To achieve the above, this thesis presents background about some representative techniques for routing and summarizes their characteristics. It then studies in detail the different factors (such as minimum area, number of vias, wire length, etc.) that affect the routing quality, and the different criteria (such as vertical/horizontal constraint graph, merging, minimal rectilinear Steiner tree, etc.) that can be used to optimize these factors. 184 pp. Englisch. Nº de ref. del artículo: 9780898382051
Cantidad disponible: 2 disponibles