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SANJAY DABRAL received his PhD in electrical engineering from Rensselaer Polytechnic Institute. An independent consultant, he is also involved in developing high-speed I/O buses.

TIMOTHY J. MALONEY has degrees in physics and electrical engineering from MIT and Cornell University. He is a Principal Engineer at Intel Corporation and has won the Intel Achievement Award for his patented ESD protection devices. A Senior Member of the IEEE, he has several patents issued and several more pending.

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The first comprehensive guide to ESD protection and I/O design

Basic ESD and I/O Design is the first book devoted to ESD (electrostatic discharge) protection and input/output design. Addressing the growing demand in industry for high-speed I/O designs, it bridges the gap between ESD research and current VLSI design practices and provides a much-needed reference for practicing engineers who are frequently called upon to learn the subject on the job.

This volume presents an integrated treatment of ESD, I/O, and process parameter interactions that both I/O designers and process designers can use. It examines key factors in I/O and ESD design and testing, and helps the reader consider ESD and reliability issues up front when making I/O choices. Emphasizing clarity and simplicity, this book focuses on design principles that can be applied widely as this dynamic field continues to evolve. Basic ESD and I/O Design:

• Describes strategies for design-oriented ESD protection
• Explains layout methods that enhance ESD protection designs
• Addresses basic I/O designs, including new problems such as mixed voltage interfaces
• Discusses fabrication aspects affecting ESD and I/O protection
• Illustrates concepts using numerous figures and examples
• Expresses device physics in terms of simple electrical circuit models
• Cross-references the material to standard texts in the field

Essential for engineers in industry and anyone designing circuits, systems, or devices for future technologies, Basic ESD and I/O Design is also a useful reference for researchers and graduate students involved in core VLSI design or computer architecture.