Reliability Prediction from Burn-In Data Fit to Reliability Models - Tapa blanda

Acerca del autor

Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.

De la contraportada

This work will educate chip and system designers in a method for accurately predicting circuit and system reliability in order to estimate failures that will occur as a function of operating conditions at the chip level. Currently, chip suppliers perform HTOL end-of-life testing as part of their standard qualification procedure, and make accurate reliability predictions based on this. However, this knowledge is often presented to designers and manufacturers with little explanation of how to use it in a meaningful, practical way. This book combines the knowledge found in many reliability publications and illustrates how to use the information presented by semiconductor manufacturing companies and chip suppliers, and make accurate reliability predictions. It allows chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature, to include reliability calculations and test results in their designs, to make meaningful reliability predictions, and to make accurate failure rate calculations for warranty period replacement costs. All of this also means that users will ultimately have control of reliability and performance in their design.

The book is aimed at chip designers and manufacturers, electronic and microelectronic system designers and reliability engineers in electronics companies. It will also be of value to academics and researchers studying microelectronics failure mechanisms.