Publicado por LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: Revaluation Books, Exeter, Reino Unido
EUR 60,89
Cantidad disponible: 1 disponibles
Añadir al carritoPaperback. Condición: Brand New. 52 pages. 8.66x5.91x0.12 inches. In Stock.
Publicado por LAP LAMBERT Academic Publishing Apr 2018, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
EUR 35,90
Cantidad disponible: 2 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. Neuware -This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.Books on Demand GmbH, Überseering 33, 22297 Hamburg 52 pp. Englisch.
Publicado por LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: preigu, Osnabrück, Alemania
EUR 33,85
Cantidad disponible: 5 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. ASIC Implementation of Low Power FP-AU using Reversible Logic | Floating Point (FP)-Arithmetic Units (AU) | Vijeyakumar Krishnasamy Natarajan (u. a.) | Taschenbuch | 52 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139587056 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.
Publicado por LAP LAMBERT Academic Publishing Apr 2018, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
EUR 35,90
Cantidad disponible: 2 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work. 52 pp. Englisch.
Publicado por LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: moluna, Greven, Alemania
EUR 31,27
Cantidad disponible: Más de 20 disponibles
Añadir al carritoCondición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Krishnasamy Natarajan VijeyakumarDr.K.N. Vijeyakumar is working as an Associate Professor in Dr.Mahalingam College of Engineering and Technology, Coimbatore, Tamilnadu. His area of interest include ASIC design, low power VLSI design.
Publicado por LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139587050 ISBN 13: 9786139587056
Idioma: Inglés
Librería: AHA-BUCH GmbH, Einbeck, Alemania
EUR 37,20
Cantidad disponible: 1 disponibles
Añadir al carritoTaschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book gives an insight into design of VLSI architectures for floating point arthimetic units using reversible logic for low power applications. Chapter 1 briefs the significance of reversible logic. Chapter 2 discusses various approaches in design of reversible arithmetic circuits. Chapter 3 describes the realization of basic gates in reversible logic. ASIC design of reversible floating point adder is discussed in chapter 4. In Chapter 5 ASIC design of reversible floating point multiplier is deliberated. Finally, chapter 6 concludes the work.