9786207460427 - Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems de Rajesh, B. Babu; Someswar, Prof. Dr. G. Manoj; Krishnanaik, Dr.... (8 resultados)

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Taschenbuch. Condición: Neu. Design of Power Reduction in Very Large Scale Integrated Systems | Power Reduction In VLSI Systems | B. Babu Rajesh (u. a.) | Taschenbuch | Englisch | 2024 | LAP LAMBERT Academic Publishing | EAN 9786207460427 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.

Taschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 296 pp. Englisch.

Kartoniert / Broschiert. Condición: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level.

Condición: New. Print on Demand.

Condición: New. PRINT ON DEMAND.

Taschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 296 pp. Englisch.

Taschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.