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ISBN 10: 3846554634 ISBN 13: 9783846554630
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Publicado por LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
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Idioma: Inglés
Publicado por Lap Lambert Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
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Añadir al carritoPaperback. Condición: Brand New. 192 pages. 8.66x5.91x0.44 inches. In Stock.
Idioma: Inglés
Publicado por Lap Lambert Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: Revaluation Books, Exeter, Reino Unido
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Idioma: Inglés
Publicado por LAP LAMBERT Academic Publishing Nov 2011, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Alemania
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Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories. 192 pp. Englisch.
Idioma: Inglés
Publicado por LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: Majestic Books, Hounslow, Reino Unido
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Idioma: Inglés
Publicado por LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: Biblios, Frankfurt am main, HESSE, Alemania
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Publicado por LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: preigu, Osnabrück, Alemania
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Añadir al carritoTaschenbuch. Condición: Neu. Approaches for Hardware Fault Mitigation in Multicore Processors | Resilient systems with unreliable devices | Daniel Sánchez | Taschenbuch | 192 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783846554630 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.
Idioma: Inglés
Publicado por LAP LAMBERT Academic Publishing Nov 2011, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: buchversandmimpf2000, Emtmannsberg, BAYE, Alemania
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Añadir al carritoTaschenbuch. Condición: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 192 pp. Englisch.
Idioma: Inglés
Publicado por LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3846554634 ISBN 13: 9783846554630
Librería: AHA-BUCH GmbH, Einbeck, Alemania
EUR 68,00
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Añadir al carritoTaschenbuch. Condición: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.